In dynamic random access memory (DRAM) integrated circuit devices, DRAM cell arrays are typically arranged in rows and columns such that a particular DRAM cell is addressed by specifying its row and column within the array. A wordline connects a row of cells to a set of bitline sense amplifiers that detect the data in the cells. In a read operation, a subset of the data in the sense amplifiers is then chosen, or “column-selected” for output of the data. DRAM cells are “dynamic” in the sense that the stored data, typically in the form of stored electrical charge on storage capacitors, will dissipate after a relatively short period of time. Thus, in order to retain the information, the contents of the DRAM cells must be periodically refreshed. The charged or discharged state of the storage capacitor must be reapplied to an individual memory cell in a repetitive manner. The maximum amount of time allowable between refreshing operations is determined by the charge storage capabilities of the capacitors that make up the DRAM cell array. DRAM manufacturers typically specify a refresh time for which it guarantees data retention in the DRAM cells.
A refresh operation is similar to a read operation, but no data is output from the bitline sense amplifiers. The sensing of the data in the cells by the sense amplifiers is followed by a restoring operation that results in the data being rewritten to the cells. The data is, thus, “refreshed”. The refresh operation is performed by enabling a wordline according to a row address, and enabling a sense amplifier. In addition, the refresh operation may be carried out by operating the sense amplifier without receiving an external refresh address. In this case, a refresh address counter that is integrated in a DRAM chip generates a row address subsequent to receiving an external start address.
In general, refresh operations can be categorized as “auto-refresh” and “self-refresh”. The auto-refresh operation occurs when, during operation of the chip, a refresh command is periodically generated and received. During auto-refresh, the receipt of other commands to the chip is interrupted and refresh is carried out. Then, the chip is allowed to receive and act on the other commands. The self-refresh operation performs refresh operations within the DRAM when in a sleep or standby mode to retain the data written in its memory cells. Those skilled in the art understand that a sleep mode is typically a low power consumption operation mode of the device where no operations are or will be executed.
In order to perform the self-refresh operation, regular internal reading of cell data and rewriting of that data are established in order to prevent data loss when the chip is operating in a so-called “sleep” mode. An internal timer controls the frequency of self-refresh. The self-refresh control circuitry is comprised of an internal oscillator, a frequency divider and a refresh count request block. Temperature monitoring and variable refresh rate control circuitry can be included. In known DRAM integrated circuits having a self-refresh function, the device is automatically switched to a self-refresh mode to perform self-refresh when required.
In order to obtain high-speed operation and high-density integrated circuits, deep sub-micron CMOS processes such as 90 nm, 65 nm and 45 nm have been introduced and used to implement many semiconductor IC devices. For those deep sub-micron processes, MOS transistors are scaled down (i.e., have minimum transistor dimensions decreased) and their threshold voltage (Vth) are lowered. However, the lowered threshold voltage results in significant sub-threshold leakage (i.e., leakage current present for transistor gate voltages below a threshold voltage) and therefore, semiconductor ICs based on such lowered threshold voltages can consume more power in normal operation as well as in a power saving mode of operation. Since a DRAM cell includes a minimally sized access transistor for coupling the storage capacitor to a bitline, the stored charge can quickly leak from the storage capacitor through this access transistor. Therefore, more frequent “self-refresh” operations are required.
FIG. 1A shows a self-refresh controller found in conventional DRAMs and FIG. 1B shows the relative timing sequence for the signals of the DRAM device shown in FIG. 1A. Referring to FIGS. 1A and 1B, a “self-refresh” mode, also known as a “sleep” mode, can be activated by a command signal 111. In response to the command signal 111 having a self-refresh entry command “SELF-REF ENTRY”, a self-refresh mode detector 113 enables a self-refresh mode signal 115 so as to be active “high” (i.e., “high” logic level voltage Vdd). In response to the “high” self-refresh mode signal 115, an internal oscillator 117 is initiated to commence the generation of a self-refresh oscillation signal 119 having a predetermined pulse period Tosc and pulse width Twosc. The oscillation signal 119 is combined with other signals by a self-refresh request generator 121 which in turn generates a self-refresh request oscillation signal 123. The request signal 123 enables an internal row-address counter 125 to generate an address signal 127 having an appropriate internal row address. A row-address decoder 129 decodes the internal row address to provide a decoded address signal 131, with the result that a selected wordline is activated. When the self-refresh mode detector 113 receives a self-refresh exit command “SELF-REF EXIT” on the command signal 111, the self-refresh mode signal 115 goes “low” (i.e., “low” logic level voltage Vss) and the internal oscillator 117 is disabled, with the result that the generation of the oscillation signal 119 is ceased. Thereafter, the self-refresh request signal 123 is no longer provided to refresh the DRAM memory cells.
The self-refresh controller in the conventional DRAM includes a compensation controller 141 that receives a compensation signal 143. The compensation controller 141 provides a control signal 145 to the internal oscillator 117 to adjust the oscillation pulse period TOSC to cover a wide range of DRAM cell retention time varied by temperature. Generally, the higher temperature, the higher frequency refresh is required and the lower temperature, the less frequency refresh is required. If the compensation signal 143 includes information on a change to the device temperature, the internal oscillator 117 adjusts or varies the pulse period TOSC. In response to the device temperature, the self-refresh repetition rate (which directly relates to the pulse period TOSC) is variably controlled (“temperature compensated self-refresh (TCSR)”). The self-refresh repetition rate can thus be varied to be longer when the device temperature drops below nominal, and varied to be shorter when the device temperature increases above nominal, due to the dependence of current leakage on temperature of the device.
Diverse types of memory cells can be used as DRAM cells. For example, metal-insulator-metal (MIM) cells are now used in memory devices, especially for logic based embedded memories. For example, in a case of a 90 nm process, trench cell based DRAM devices have a relatively large capacitance of 20 fF. On the other hand, the MIM capacitor cell has a capacitance of 6 fF. Unlike stacked or trench cells, the MIM cells do not ensure long enough refresh characteristics, due to the small capacitances and high leakage inherent in logic-based processes. Therefore, efforts have been made to enhance the refresh characteristics of the MIM cells. In logic implementations, uncertainty of refresh characteristics and current leakage makes it difficult to increase relevant logic blocks in DRAM chips. Now, DRAM devices are widely used in mobile products wherein longer battery life is required. In mobile products, the TCSR function is now surging as one of the supplementary features in order to extend the battery life. The TCSR function controls the refresh time period based on the temperature experienced by the device, such as a mobile product. The characteristics from the cell processes and the environment temperature are two separate factors which can dynamically require changes the refresh time period.
The memory cells limited to a small capacitance, like MIM cells, can easily lose data polarity in a short period of time. Hence, the relevant circuits should have flexibility to change or adjust the refresh time period in order to cover all probable refresh time characteristics. Solutions for this issue can increase the amount of logic circuitry and its complexity when the TCSR function is adopted as one of features. It is well known that the refresh time becomes worse exponentially with temperature. Therefore, there are two factors which can change the refresh time period, that is, temperature and inherent refresh characteristics caused by unavoidable process variations and defect-oriented problems.
The problem is addressed and discussed by (i) S. Takase et al. “A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme”, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1600-1606, November 1999, IEEE Journal of Solid-State Circuits; (ii) Y. Idei et al., “Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register”, IEEE Journal of Solid-State Circuits, vol. 33, pp. 253-259, February 1998; and (iii) T. Tsuruda et al., “High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's”, IEEE Journal of Solid-State Circuits, vol. 32, pp. 477-482, March 1997. They show how to generate self-refresh time and characteristics of cell refresh time according to leakage level and temperature. They do not, however, mention any TCSR issue that is main features in mobile products and how to combine two refresh time change factors. Conventionally, the TCSR and the refresh time characteristics have been considered as separate issues, each with separate and independent solutions.
It is, therefore, desirable to provide a merged logic approach for these two separate issues without a large area penalty caused by an independent logic solution. It is desirable to provide memory devices having DRAM cells with diverse refresh time characteristics and the TCSR function.